1. Field of the Invention
This invention relates to a coding apparatus for coding a motion picture, and more particularly to a video rate compressing and reproducing apparatus for storage media for use with a video mail system, a video tape recorder and so forth.
2. Description of the Related Art
High efficiency coding is applied to a video signal in order to store the video signal into a digital storage medium of a comparatively narrow band such as a compact disk (CD). An investigation of the International Standardization Organization ISO-IEC JTC1/SC2/WG11 (hereinafter referred to as MPEG (Motion Picture Expert Group) as commonly called) is directed to coding systems for media of 1.5 Mbps. An outline of the investigated systems is described, for example, in Journal of Image electronics Society, Vol. 20, No. 4, pp.306-316. According to the document, it is forecast for hybrid coding including a combination of discrete cosine transform (DCT), quantization and variable length coding with motion compensated inter-frame prediction, to be adopted as an international standard. While the basic scheme of the MPEG system is similar to that of the CCITT H.261 document which has been internationally standardized already for the object of an application to motion picture communications, it employs inter-frame prediction in which bidirectionally predictive coding (B-picture) into which backward prediction is included is incorporated in addition to intra-coding (I-picture) and predictive coding (P-picture). Further, enhancement of the coding efficiency is anticipated by raising the accuracy of motion vectors for use for motion compensation up to the accuracy of a half picture element. Since the amount of processing required for coding and the required memory capacity are increased remarkably comparing with those required for realization of an apparatus of the CCITT H261 standard in order to achieve the enhancement of the performance described above, much contrivance is required for realization of the coding apparatus.
One of possible solutions to realization of a picture coding apparatus based on the MPEG system using the current technology is to employ a chip set for image signal processing on the market. A chip set for commercial use is available from Graphics Communication Technologies (GCT). Functions of the individual chips of the chip set are described in Nikkei Electronics, Jul. 25, 1990, pp.209-222. According to the description, the chip set provides individual processing functions such as motion vector detection, DCT, inverse DCT, quantization, inverse quantization, variable length coding and variable length decoding as chips for exclusive use so that a coding apparatus of the CCITT H.261 standard may be constituted from a combination of the processing functions.
However, in order to realize, using the chip set described above, forward/backward inter-frame prediction or vector detection of the half picture element accuracy, which is required newly by the MPEG system, at a video rate, it cannot be avoided to cause a large number of chips to operate in parallel to one another, which gives rise to a problem that the apparatus cost is increased. Another problem resides in that, since the coding chip and the decoding chip are provided separately, if a decoding function is incorporated in a coding apparatus, then this will lead to an increase of the number of processing chips.
In order to allow a coding apparatus for a storage medium of a video rate for use with authoring, a video mail, a digital video tape recorder or the like to be provided at a low cost, first it is necessary to replace processing functions, which cannot be realized efficiently by an existing LSI (large scale integrated circuit), such as bidirectional motion compensation or vector detection of the accuracy of one picture element or less with a VLSI (very large scale integrated circuit) having a higher performance to achieve reduction of the number of parts. In fact, if the VLSI technology in recent years is used, it is not difficult itself to develop a VLSI having a required processing capacity. However, with the present LSI technology, since a frame memory circuit for holding image data cannot be built in a calculation chip, it is a premise that a system configuration employing a memory circuit in addition to a VLSI is employed. In this instance, the required speed of a memory chip or the number of chips to be adopted depend upon the frequency of accessing to the memory circuit. Accordingly, it is important to provide an optimum memory configuration to reduce the overall cost of the system.
Further, in the application system described above, the function of reproducing a motion picture from a bit sequence obtained by coding is essentially required in addition to the real time coding function, and also the function of monitoring a picture being coded is required in order to supervise an influence of compression coding upon the picture quality.